The present invention relates to semiconductor devices, and more specifically, fin-like field effect transistors (FinFET).
Fin field effect transistors (finFETs) have been extensively investigated as one of the future device options for continued scaling of complementary metal oxide semiconductor (CMOS) technology. Most CMOS applications require various types of devices on the same chip. For example, a microprocessor chip usually includes both n-type and p-type (nFETs and pFETs) devices with various threshold voltages. The finFET devices have undoped channel to take advantage of the improved Device Electrostatics. The Vt tuning in finFET devices is achieved by the smart choice of Work Function Metals during the Gate Stack Patterning.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits having finFETs with improved junction (aka Punch Through Stopper (PTS) Junction) beneath active channel regions to prevent sub-fin leakage in the bulk finFET devices.